Bringing Together the IP Community
REUSE is the first of its kind semiconductor IP trade show and conference. A grass roots effort conceived and brought to you by the IP community itself, our aim is to provide the maximum value for both IP suppliers and customers in a forum for learning, sharing, and networking.
About the Event
REUSE 2016 is the first of an annual conference and trade show to bring together the semiconductor IP supply chain and its customers for a full day of everything to do with semiconductor IP. Hosted in the heart of Silicon Valley at the world famous Computer History Museum, there could not be a more appropriate venue for a day focused on the hottest segment of the semiconductor industry.
The day will begin with a keynote address from Jim Feldhan, President of Semico Research on Trends driving IP reuse followed by multiple tracks of technical and business-oriented talks by a diverse set of companies, large and small. The closing keynote presentation “A Vibrant 3rd Party IP Ecosystem is Critical to the Growth of the Semiconductor Industry” will be delivered by Taher Madraswala, President and CEO of Open Silicon.
Customer may engage with suppliers is a spacious exhibit area to learn about new technology and solutions that are available.
Capping off the evening will be a social in the exhibit hall with drinks and food provided to allow everyone the opportunity to relax and meet new friends, and even tour the museum itself.
Speakers
Meet our most valued speakers
Schedule
Welcome to REUSE 2016
Trends Driving Reuse
Embedded FPGAs for Architects & Physical Designers
Embedded FPGAs can provide flexibility, add value, and increase the ROI of your chip designs from IoT/MCU to Networking.
With Embedded FPGAs you can customize one chip to meet many applications/customer needs and/or evolve the chip to keep up, in-system, with changing protocols and standards.
Tony Kozaczuk, Director of Solutions Architecture, will summarize multiple use cases:
- easy I/O pin multiplexing: reduce risk and increase the ability to observe more signals, programmably changeable in minutes
- programmable serial I/O
- programmable accelerators
- extending battery life using embedded FPGA to offload tasks from the processor
- programmable networking chips for Data Centers
- fast, reconfigurable control logic up to ~1GHz in TSMC16FF+/FFC
- what are the specific deliverables
- how to do resource and floor planning
- how to use LEF
- integrating GDS of the embedded FPGA
- metal stack up
- clock
- power grid connectivity
- how we prove out our hard IP in our validation chip architecture Tony Kozaczuk and Abhijit Abhyankar
Using GZIP Data Compression to Reduce Power Consumption in IoT Devices
IP helped designers of first-generation IoT devices achieve their primary goal of getting to market quickly. Now second-generation IoT device designers must do more, differentiating their products from competitors by reducing power requirements, lowering costs, and providing more processing power in edge devices. Lossless compression IP implementing a widely accepted standard such as GZIP can help in all three of these areas. Here we will focus on one area, power reduction, and through examples show power calculations with and without data compression for firmware code shadowing, data storage, and RF networking. We will further show that the small size and low latency of good digital compression IP makes it a viable and relatively easy way to significantly reduce a system’s power requirements in IoT products from individual sensor devices to edge analytics in gateways and servers.
Meredith LuckyIO Library Reuse: Fear not to Customize!
Cost, Power, Feature Set, Reliability, Performance. These are key factors that go into designing and marketing a competitive semiconductor product. Rarely, however, do design teams leverage an asset that can have some of the greatest impact on these factors: Custom IO. The IO Library a team chooses to use can have larger impact on die area, power, feature set and other factors, more so than most other individual IP blocks. Yet few companies look to custom IO as an option. Most are content to use whatever the foundries offer for free. The interesting thing however is that every top 10 semiconductor company has their own internal IO development team Why? Because they realize that they can gain a huge competitive advantage by optimizing their IO. Find out how 3rd party IO Libraries, and especially IO customization, can give your product, at reasonable cost, the completive advantage you need-- and minimize all risk at the same time.
Stephen FairbanksPanel : Are You Receiving Full Value for Your IP?
The Secrets to Building IP
Meeting customers’ needs with standardized solutions requires highly programmable designs that are easily re-targeted to process variants, including metal stacks, IO voltages and Vt selections, as well as completely different foundries and process nodes. TCI employs a range of fascinating techniques, from building robust circuits to using proprietary extensions of CAD tools to creating designs and deliverables from one, universal database. In this presentation John will explain the engineering behind a highly automated CAD flow that enables TCI to maximize IP consistency, quality and reuse.
Dr. John ManeatisBuilding a Silicon Area Optimized Multi-format Video Encoder IP
This presentation discusses the history of various video encoding standards, their relevance today and the impact of ever growing resolution and frame rate requirements on power, performance and silicon area. Allegro DVT presents how to build a silicon area optimized multi-format encoder IP while maintaining an excellent video encoding quality and low power consumption even for Ultra HD resolutions.
Tomi JalonenProtecting your IP with Digital Fingerprints
Efforts undertaken by the industry to protect semiconductor IP have largely been incomplete and ineffective in being able to assist IP companies in protecting their valuable assets. Furthermore, with the explosion in the amount of IP being licensed, semiconductor companies are now exposed to significant liabilities as a result of mistakes made by their engineering teams in reusing internal and third-party IP without the proper licenses in place. In this session, we will discuss the problem facing the industry today, current methods, and a new technology called Fingerprinting that provides a completely new approach to solving this decades old problem.
Warren SavageIoT: Poised to offer huge growth opportunities for the global IP Business
A Vibrant 3rd Party IP Ecosystem is Critical to the Growth of the Semiconductor Industry
The third-party IP ecosystem plays a critical role in the growth of the semiconductor industry. Taher Madraswala, president and CEO of Open-Silicon, will discuss the state of the IP market and how the functional integration of IPs is driving new market applications. He will discuss the importance of choosing the right IPs in order to achieve first time silicon success, as well as the benefits of leveraging third-party IP compared to internal IP development. Taher will describe case studies of complex SoCs, completed for leading OEMs, that were highly successful through leveraging the third-party IP ecosystem. Designers are finding new ways to produce less expensive SoCs with 2.5D interposer based system-in-package (SiP) designs, which enable a mix and match of chip/IP components at optimum process nodes. This approach will greatly increase the reuse of IP developed at older process nodes. Additionally, as IP integration costs are increasing due to the rising number of discrete IP blocks in the current generation of SoCs, designers are leveraging IP subsystem-based design methodologies to lower development cost and risk. Continued developments in the third-party IP ecosystem, for new trends like 2.5D SiP and IP subsystems, will enable the semiconductor industry to continue to innovate and evolve.
Taher MadraswalaEvent registration & Breakfast
Come early for some coffee some light pastries and good conversation before the keynote begins.
Can your SOC keep its secrets?
Aside from ever growing complexity (gate count, increasing IP core use, etc.) there is an increasing need for SOC security especially in context of IoT devices. IoT devices have proven to be an easier target for malicious hacking attempts. Recent high profile security breaches (recent web-site outages (DSoS, DNS), Target credit card breach, etc.) have shown the vulnerabilities of connected devices. The need for a secure non-volatile memory is evident. This presentation provides an overview on available options for use of on-chip IP to securely store sensitive data and keys.
Bernd StammeHBM2 IP Subsystem Solution for High Bandwidth Memory Applications
The most common memory requirements for emerging applications, such as high performance computing, networking, deep learning, virtual reality, gaming, cloud computing and data centers, are high bandwidth and density based on real-time random operations. High Bandwidth Memory (HBM2) meets this requirement and delivers unprecedented bandwidth, power efficiency and small form factor. HBM2 (X1024) offers the maximum possible bandwidth of up to 256 GBps compared to 4GBps with DDR3 (X16) at 1/3rd of the power efficiency. HBM2 and 2.5D silicon interposer integration unlock new system architectures, therefore, causing HBM2 ASIC SiP (system-in-package) to gain popularity among OEMs. One of the key IPs used to develop these ASIC SiPs is the HBM IP subsystem that consists of controller, PHY and die2die I/O. Open-Silicon’s HBM2 IP subsystem fully complies with the HBM2 JEDEC® standard. The IP translates user requests into HBM command sequences (ACT, Pre-Charge) and handles memory refresh, bank/page management and power management on the interface. The high performance, low latency controller leverages the HBM parallel architecture and protocol efficiency to achieve maximum bandwidth. The IP includes a scalable and optimized PHY and die-to-die I/O needed to drive the interface between the logic-die and the memory die-stack on the 2.5D silicon interposer. Open-Silicon’s HBM2 IP subsystem addresses the implementation challenges associated with interoperability, 2.5D design, overall SiP design, packaging, test and manufacturing. Multiple built-in test and diagnostic features, such as probe pads and loop-back for issue-isolation within the various IP subsystem components, not only address the test and debug challenges, but help in yield management and yield improvement, while ramping HBM2 ASIC designs into volume production. Open-Silicon’s HBM2 first implementation solution in TSMC 16nm FF+ features 2Gbps per pin data rate at up to 5mm trace length. This enables a full 8-channel connection from a 16nm SoC to a single HBM2 memory stack at 2Gbps, achieving bandwidths up to 256GB/s.
Dhananjay WaghWhy is Chip Design so Hard?
To the non-experienced company needing a custom chip, ASIC or SOC for their new “bright idea” IoT product and to their engineers, the task of developing, manufacturing, and getting the chip delivered is daunting. This talk will outline the overwhelming number of tools, skill sets, costs, IP acquisition and industry associations needed to navigate the chip design and delivery process. The presentation will also, take a look at how the industry presently supports new chip development and where it needs to go in the future to streamline the process for the non-experienced companies that will no doubt fuel the IoT boom when it truly comes.
Jim BruisterChoosing the Right IP Cores for Low-Latency Video Streaming
A negligible delay from video capture to display—the “glass-to-glass” latency—is critical for many video streaming applications, from advanced driver assistant systems (ADAS) and unmanned vehicles to video conferencing and broadcasting. Choosing the IP cores that will enable a successful low-latency video system is not a trivial task: designers must first understand the factors that impact latency, then select cores that provide adequate control over the latency-critical functions. In this presentation, we will apply these considerations to a typical end-to-end video streaming system, providing guidance on avoiding latency pitfalls and explaining how glass-to-glass latency depends largely on the rate control attributes of the system’s video compression cores.
Dr. Nikos ZervasEmbedded FPGA Can Extend Your Battery Life
Tony Kozaczuk, Director of Solutions Architecture, will detail an example of how a small amount of embedded FPGA in TSMC40ULP can extend battery life 2-5x compared to an ARM processor. An ARM processor needs to do many memory accesses to execute code and process data which drives up energy use. EFLX embedded FPGA can do several basic DSP tasks at lower energy and in less time. The embedded FPGA can be used as an “always on” processor to offload the ARM core, only waking it up when needed for less repetitive tasks. Tony will show the RTL code (available separately after the presentation) and detail the calculations involved in the analysis.
Tony KozaczukTiming IP challenges in the modern SoC
Today's SoC will have an array of timing needs to support a wide variety of applications and requirements. In this presentation, Brian will outline several of the most common timing challenges, and explain how timing IP is used to address them. He will cover basic clock generation and timing closure, jitter filtering, delay lines (DLLs), and low jitter requirements for common interfaces.
Brian GardnerDebug for 21st century: Solving Systemic Complexity for SoCs, heterogenous multi-core (and RISC-v)
Modern SoCs are staggeringly complex: billions of transistors and design costs of many tens of millions of dollars. The trend to IP blocks has certainly made it easier to design such incredible chips, re-using proven sub-systems. But there are still major problems one level up in abstraction: systemic complexity, interactions between blocks, HW/SW integration challenges, system-level validation, etc.
That requires tools that operate at the system level, not at the gate or signal level: protocol aware monitors, transaction level analysis and the ability to coordinate and reconcile information across the whole of a complex SoC, both hardware and sod software. UltraSoC will be discussing these issues.
Rupert BainesUltra-low Power SRAM for IOT to Enterprise
Today’s advanced SOCs contain large amounts of SRAM in all sorts of shapes and sizes. There are literally hundreds of SRAM blocks typically consuming greater than 60% silicon area and power. The increasing need for “always-on” functionality only serves to magnify the power problem. For IOT applications battery life is critical, so reducing SRAM power is paramount. SureCore has developed an Ultra-Low Power SRAM IP that enables a new generation of IC designs. Their industry-leading, low power SRAM technology is process independent and variability tolerant, making it especially suitable for leading edge silicon process nodes from 40nm down to 7nm. sureCore Ultra-Low Power SRAM IP empowers SoC developers to meet both challenging power budgets and manufacturability constraints posed by applications ranging from IOT to Enterprise.
Joel RosenbergExhibitors
Look who you will meet at REUSE 2016
Sponsors and Partners
